1. Field of the Disclosure
The present invention relates to nonvolatile ferroelectric memory control devices, and more particularly, to a nonvolatile ferroelectric memory control device configured to control an internal memory dump when a ferroelectric memory is used for internal memory in a SOC (system on a chip) structure.
2. Description of the Related Art
Generally, a ferroelectric random access memory (hereinafter, referred to as xe2x80x98FRAMxe2x80x99) has attracted considerable attention as a next generation memory device because it has a data processing speed as fast as a Dynamic Random Access Memory DRAM and conserves data even after the power is turned off.
The FRAM includes capacitors similar to the DRAM, but the capacitors have a ferroelectric substance for utilizing the characteristic of a high residual polarization of the ferroelectric substance in which data is not low even after eliminating an electric field applied thereto.
FIG. 1 is a characteristic curve illustrating a, hysteresis loop of a general ferroelectric substance.
As shown in FIG. 1, a polarization induced by an electric field does not vanish but remains at a certain portion (xe2x80x98dxe2x80x99 or xe2x80x98axe2x80x99 state) even after the electric field is cleared due to existence of a residual (or spontaneous) polarization. These xe2x80x98dxe2x80x99 and xe2x80x98axe2x80x99 states may be matched to binary values of xe2x80x981xe2x80x99 and xe2x80x980xe2x80x99 for use as a memory cell.
FIG. 2 is a structural diagram illustrating a unit cell of the FRAM device.
As shown in FIG. 2, the unit cell of the conventional FRAM is provided with a bitline B/L arranged in one direction and a wordline W/L arranged in another direction vertical to the bitline B/L. A plateline P/L is arranged parallel to the wordline and spaced at a predetermined interval.
The unit cell is also provided with a transistor T1 having a gate connected to an adjacent wordline W/L and a source connected to an adjacent bitline B/L, and a ferroelectric capacitor FC1 having a first terminal of the two terminals connected to a drain terminal of the transistor T1 and a second terminal of the two terminals connected to the plateline P/L.
The data input/output operation of the conventional FRAM is now described referring to FIGS. 3a and 3b. 
FIG. 3a is a timing diagram illustrating a write mode of the FRAM.
Referring to FIG. 3a, when a chip enable signal CSBpad applied externally transits from a high to low level and simultaneously a write enable signal WEBpad also transits from a high to low level, the array is enabled to start a write mode. Thereafter, when an address is decoded in a write mode, a pulse applied to a corresponding wordline transits from a xe2x80x9clowxe2x80x9d to xe2x80x9chighxe2x80x9d level, thereby selecting the cell.
In the interval where the wordline WL is held at a high level, a high signal of a predetermined interval and a low signal of a predetermined signal are sequentially applied to a corresponding plateline PL. In order to write binary logic values xe2x80x981xe2x80x99 or xe2x80x980xe2x80x99 in the selected cell, xe2x80x98highxe2x80x99 or xe2x80x98lowxe2x80x99 signals synchronized with the write enable signal WEBpad are applied to a corresponding bitline B/L.
In other words, when a high signal is applied to a bitline BL and a low signal is applied to a plateline PL, a logic value xe2x80x9c1xe2x80x9d is written in the ferroelectric capacitor FC1. When a low signal is applied to a bitline BL and a high signal is applied to a plateline PL, a logic value xe2x80x9c0xe2x80x9d is written in the ferroelectric capacitor FC1.
FIG. 3b is a timing diagram illustrating a read mode of the FRAM.
Referring to FIG. 3b, when a chip enable signal CSBpad externally transits from a xe2x80x9chighxe2x80x9d to xe2x80x9clowxe2x80x9d level, all bitlines are equalized to a xe2x80x9clowxe2x80x9d level by an equalization signal before a required wordline is selected.
After each bitline is deactivated, an address is decoded to transit a signal on the required wordline from a xe2x80x9clowxe2x80x9d to xe2x80x9chighxe2x80x9d level, thereby selecting a corresponding unit cell. A xe2x80x9chighxe2x80x9d signal is applied to a plateline of the selected cell to destroy a data Qs corresponding to the logic value xe2x80x9c1xe2x80x9d stored in the FRAM.
If a logic value xe2x80x9c0xe2x80x9d is stored in the FRAM, its corresponding data Qns will not be destroyed. In this way, the destroyed and non-destroyed data output different values, respectively, according to the above-described hysteresis loop characteristics. As a result, a sense amplifier senses logic values xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d.
In other words, as shown in the hysteresis loop of FIG. 1, the state moves from the xe2x80x98dxe2x80x99 to xe2x80x98fxe2x80x99 when the data is destroyed while the state moves from xe2x80x98axe2x80x99 to xe2x80x98fxe2x80x99 when the data is not destroyed. As a result, after the lapse of a predetermined time, the sense amplifier is enabled by the sense amplifier enable signal SEN. The sense amplifier outputs a logic value xe2x80x9c1xe2x80x9d when the data is destroyed, and the sense amplifier outputs a logic value xe2x80x9c0xe2x80x9d when the data is not destroyed.
After the sense amplifier amplifies and outputs the data, the data should be recovered into the original data. Accordingly, when a xe2x80x9chighxe2x80x9d signal is applied to the required wordline, the plateline is deactivated from xe2x80x9chighxe2x80x9d to xe2x80x9clowxe2x80x9d.
A conventional system on a chip xe2x80x98SOCxe2x80x99 structure using the above-described ferroelectric memory automatically separated the memory into an internal region and an external region.
The internal memory region using internal addresses and the external memory region using external addresses are previously set using a physical method on a SOC when address size is determined. For example, if an internal memory has the size of 4K bite, an internal memory is used in an address region of A11, A10, . . . , A0. An external expansion memory is automatically used in an address region having the size of more than 4 K bite.
In other words, once the address size of an internal memory in the SOC is set up, then internal and external address regions are automatically determined. As a result, data of the internal memory cannot be externally outputted via input/output ports in the external address region.
FIG. 4 is a diagram for explaining operations of data input/output port in a dump mode of a conventional SOC.
The dump mode is to sequentially output internal memory data via data input/output port to the outside. In a dump mode, an internal memory data DATA less than mxe2x88x921 greater than  is allotted to an internal address ADD less than m greater than . A memory data DATA less than m greater than  of the final internal address region ADD less than m greater than  is outputted from the next address ADD less than m+1 greater than , the first external address. An internal address valid signal ADD_Valid to set a limit of internal address region is effective to the final internal address ADD less than m greater than . Since an address, ADD less than m+1 greater than  where the final internal memory data DATA less than m greater than  is outputted is the external address region ADD less than m+1 greater than , the final internal data DATA less than m greater than  is not outputted via a data input/output port.
As a result, memory data of the final internal address region in a boundary region between the internal address region and the external address region is not dumped during the internal memory dump mode.
Additionally, a logic for determining the size of memory address and for testing the memory address is realized with a metal option, which is a hardware-connection of metal layers to power lines. When the memory size is changed, a metal mask layer of SOC should be also changed. As a result, the process becomes complicated and the cost increases.
Accordingly, it is an object of the present invention to make the data in the internal addresses be normally outputted via a data input/output port by allotting external memory region to internal memory region in a dump mode.
It is another object of the present invention to easily change the memory size by programming the memory site using a FRAM code cell.